AN4664

1.3.2.2.2 PCIe_Tx_PLL_0

The PCIe_Tx_PLL_0 (Transmit PLL) is configured for a 100 MHz Reference Clock and a 5000 Mbps Desired Output Bit Clock.

The PolarFire FPGA transceiver is a half-rate architecture that is the internal high-speed path that uses both edges of the clock to keep the clock rates down. Therefore, the clock can run at half of the data rate, thereby consuming less dynamic power. The transceiver in PCIe mode requires a 2500 MHz bit clock.

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