1.3.2.2.4 PCIeM_AXI4Connect_0
(Ask a Question)The PCIeM_AXI4Connect_0 (CoreAXI4Interconnect) bus is configured for a single master and two slaves and used to connect the PF_PCIE_0 with PCIe_AXI_SRAM_0 and DDR4 for DMA operations.
The PCIeM_AXI4Connect_0 (CoreAXI4Interconnect) bus is configured for a single master and two slaves and used to connect the PF_PCIE_0 with PCIe_AXI_SRAM_0 and DDR4 for DMA operations.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.