54.10.5 Digital to Analog Converter (DAC) Characteristics

Table 54-28. Operating Conditions⁽¹⁾
Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
Res	Resolution	-	-	-	12	bits
clk	Internal DAC Clock frequency	-	-	-	12	MHz
fs_dac	Sampling frequency	clk/12, CCTRL=0x0 (Low Power)	-	-	100	ksps
fs_dac	Sampling frequency	clk/12, CCTRL=0x2 (High Power)	-	-	1	Msps
V_OUTmin	Min. Output Voltage	-	-	-	0.15	V
V_OUTmax	Max. Output Voltage	-	V_DDANA-0.15	-	-	V
V_REF	External Reference input	CTRLB.REFSEL[1:0]=0x2 (VREFAB)	1	-	V_DDANA-0.15	V
V_REF	External Reference input	CTRLB.REFSEL[1:0]=0x0 (VREFAU)	1	-	V_DDANA	V
C_VREF	External decoupling capacitor	-	-	220	-	nF
C_LOAD	Output capacitor load	-	-	-	50	pF
R_LOAD	Output resistance load	-	5	-	-	kΩ
t_s	Settling time	For reaching ±1LSB of the final value. Step size < 500 LSB - C_load = 50pF	-	-	1	µs
t_{s_FS}	Settling time 0x080 to 0xF7F	For reaching ±1LSB of the final value. Step size from 0% to 100% - C_load = 50pF	-	5	7	µs

Note:

These values are based on simulation. They are not covered by production test limits or characterization.

Table 54-29. Differential Mode⁽¹⁾
Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
INL	Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F	i12clk = 12 MHz, V_DDANA = 3.0V, External Ref. = 2.0V, C_LOAD = 50 pF	-	±2.4	±3.4	LSB
INL	Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F	i12clk = 12 MHz, V_DDANA = 3.0V, Internal Ref, C_LOAD = 50 pF	-	±3.2	±4.2	LSB
DNL	Differential Non Linearity, Best-fit curve from 0x080 to 0xF7F	i12clk = 12 MHz, V_DDANA = 3.0V, External Ref. = 2.0V, C_LOAD = 50 pF	-	±2.4	±3.6	LSB
DNL		i12clk = 12 MHz, V_DDANA = 3.0V, Internal Ref, C_LOAD = 50 pF	-	±3.5	±5.4	LSB
Gerr	Gain Error	External Reference voltage	-	±0.4	±1.7	% FSR
Gerr	Gain Error	1.0V Internal Reference voltage	-	±0.8	±7.0	% FSR
Offerr	Offset Error	External Reference voltage	-	±13	±40	mV
Offerr	Offset Error	1.0V Internal Reference voltage	-	±8	±64	mV
ENOB	Effective Number Of Bits	Fs = 1 Ms/s - External Ref - CCTRL = 0x2	9.9	10.7	10.9	Bits
SNR	Signal to Noise ratio		63.5	68.6	72.6	dB
THD	Total Harmonic Distortion		-79.1	-72.5	-61.0	dB

Note:

These values are based on characterization. These values are not covered by test limits in production.

Table 54-30. Single-Ended Mode ⁽¹⁾
Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
INL	Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F	i12clk = 12 MHz, V_DDANA = 3.0V External Ref. = 2.0V, C_LOAD = 50 pF	-	±2.7	±4.0	LSB
INL	Integral Non Linearity, Best-fit curve from 0x080 to 0xF7F	i12clk = 12 MHz V_DDANA = 3.0V, Internal Ref, C_LOAD = 50 pF	-	±5.2	8.2	LSB
DNL	Differential Non Linearity, Best-fit curve from 0x080 to 0xF7F	i12clk = 12 MHz, V_DDANA = 3.0V External Ref = 2.0V, C_LOAD = 50 pF	-	±3.5	±6.1	LSB
DNL		i12clk = 12 MHz V_DDANA = 3.0V, Internal Ref, C_LOAD = 50 pF	-	±6.4	±9.4	LSB
Gerr	Gain Error	External Reference voltage	-	±0.3	±1.5	% FSR
Gerr	Gain Error	1.0V Internal Reference voltage	-	±0.8	±6.9	% FSR
Offerr	Offset Error	External Reference voltage	-	±7	±21	mV
Offerr	Offset Error	1.0V Internal Reference voltage	-	±2	±16	mV
ENOB	Effective Number of Bits	Fs = 1 Ms/s - External Ref - CCTRL = 0x2	9.1	10.3	10.7	Bits
SNR	Signal to Noise Ratio		63.5	68.6	72.6	dB
THD	Total Harmonic Distortion		-79.1	-72.8	-61.0	dB

Note:

These values are based on characterization. These values are not covered by test limits in production.

Table 54-31. Power Consumption
Symbol	Parameters	Conditions	TA	Min.	Typ.	Max.	Unit
I_DDANA	Differential Mode, DC supply current, 2 output channels - without load	fs = 1 Msps, CCTR L= 0x2, V_REF> 2.4V, V_DD= 3.3V	Max. 85°C Typ. 25°C	-	384	540	µA
		fs = 10 ksps, CCTRL = 0x0, V_REF < 2.4V, V_DD= 3.3V		-	283	411	µA
	Single-Ended Mode, DC supply current, 2 output channels - without load	fs = 1 Msps, CCTRL = 0x2, V_REF> 2.4V, V_DD = 3.3V		-	306	443	µA
		fs = 10 ksps, CCTRL = 0x0, V_REF< 2.4V, V_DD = 3.3V		-	230	332	µA

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