70.7.8 TCPC Alert Mask Register
The following configuration values are valid for all listed bit names of this register:
0: Interrupt masked.
1: Interrupt unmasked.
| Name: | TCPC_ALM |
| Offset: | 0x12 |
| Reset: | 0x0FFF |
| Property: | Read/Write |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VDA | VBUSSNKDS | FLT | VBUSLO | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VBUSHI | PWRS | CCS | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 1 | 1 |