70.7.10 TCPC Fault Status Mask Register
The following configuration values are valid for all listed bit names of this register:
0: Interrupt masked.
1: Interrupt unmasked.
Name: | TCPC_FSM |
Offset: | 0x15 |
Reset: | 0xFF |
Property: | Read/Write |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ALLREGRES | FRCOFVBUS | AUTDCHF | FRCDCHF | VBUSOCPF | VBUSOVPF | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 1 | 1 | 1 | 1 | 1 | 1 |