19.4.1.8.3 SPI Host Mode and Frame Host Mode

This Framed SPI mode is enabled by setting the MSTEN bit (SPIxCON1[5]) and the FRMEN bit (SPIxCON1[23]) to ‘1’, and the FRMSYNC bit (SPIxCON1[22]) to ‘0’. In this mode, the serial clock will be output continuously at the SCKx pin, regardless of whether the module is transmitting. When SPIxBUF is written, the SSx pin will be driven active-high or active-low, depending on the FRMPOL bit (SPIxCON1[21]), on the next transmit edge of the SCKx clock.

The SSx pin will be high for one SCKx clock cycle. The module will start transmitting data on the next transmit edge of SCKx, as shown in Figure 19-13. A connection diagram indicating signal directions for this operating mode is shown in Figure 19-13.