4.9.4.4.5 CMCR – System Clock Management Control Register
Name: | CMCR |
Offset: | 0x039 |
Reset: | 0x00 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CMCCE | CMONEN | SRCD | CCS | CMM[2:0] | |||||
Access | R/W | R/W | R | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CMCCE Clock Management Control Change Enable
1
’ to enable the change of the CMCR bits. The CMCCE bit
is only updated when the other bits in CMCR are simultaneously written to
‘0
’. CMCCE is cleared by hardware four cycles after it is
written or when CLPR.CLKPS[2:0] bits are written. Rewriting the CMCCE bit within
this time-out period neither extends the time-out period nor clears the CMCCE
bit.Bit 6 – CMONEN Clock Monitor Enable
1
’ to enable the clock monitoring, if the CMONEN bit is
written to logic ‘0
’, clock monitoring is always
disabled.Bit 5 – Reserved Bit
0
’.Bit 4 – SRCD Slow RC Oscillator Disable
SRCD | Description |
---|---|
0 | The SRC oscillator is running. |
1 | The SRC oscillator is stopped if the WDTON fuse bit is cleared (see Fuse Low Byte from Related Links.), the watchdog is disabled and no other module uses CLKSRC |
Bit 3 – CCS Core Clock Select
1
’ to enable the mode selected with the CMM[2:0] bits.
CMM[2:0] cannot be modified in this mode. If the CCS bit is written to logic
‘0
’, the FRC oscillator clock is enabled and CMM[2:0] can be
modified. If the CMM[2:0] bits in CMCR are not changing simultaneously, the CCS bit
can only be set to ‘1
’. After an external clock fail detection, the
CCS bit is written to ‘0
’.CSS | Description |
---|---|
0 | The FRC oscillator is the active clock source and generates the input clock (CL). CMM[2:0] can be modified |
1 |
The clock source selected by CMM[2:0] is active. Possible sources are: CLKEXT,CLKSRC,CLKXTO4, CLKXTO6,CLKADIV. Modification of CMM[2:0] is not possible. |
Bits 2:0 – CMM[2:0] Clock Management Mode
Clock Source for System Clock Prescaler (CL) | ||||
---|---|---|---|---|
CMM[2:0] | CCS = 0 | CCS= 1 | ||
0 | 0 | 0 | FRC | CLKSRC |
0 | 0 | 1 | FRC | CLKADIV |
0 | 1 | 0 | FRC | CLKEXT |
0 | 1 | 1 | FRC | CLKXTO6 |
1 | 0 | 0 | FRC | CLKXTO4 |
1 | 0 | 1 | FRC | CLKXTO4 |
1 | 1 | 0 | FRC | CLKXTO4 |
1 | 1 | 1 | FRC | CLKXTO4 |