4.9.4.4.5 CMCR – System Clock Management Control Register

Name: CMCR
Offset: 0x039
Reset: 0x00

Bit 76543210 
 CMCCECMONENSRCDCCSCMM[2:0] 
Access R/WR/WRR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – CMCCE Clock Management Control Change Enable

TThe CMCCE bit must be written to logic ‘1’ to enable the change of the CMCR bits. The CMCCE bit is only updated when the other bits in CMCR are simultaneously written to ‘0’. CMCCE is cleared by hardware four cycles after it is written or when CLPR.CLKPS[2:0] bits are written. Rewriting the CMCCE bit within this time-out period neither extends the time-out period nor clears the CMCCE bit.

Bit 6 – CMONEN Clock Monitor Enable

This bit controls the clock monitoring of the external clock (CLKEXT). The CMONEN bit must be written to logic ‘1’ to enable the clock monitoring, if the CMONEN bit is written to logic ‘0’, clock monitoring is always disabled.

Bit 5 –  Reserved Bit

This bit is reserved and reads as ‘0’.

Bit 4 – SRCD Slow RC Oscillator Disable

Allows the SRC oscillator to stop if it is not used.
SRCDDescription
0The SRC oscillator is running.
1The SRC oscillator is stopped if the WDTON fuse bit is cleared (see Fuse Low Byte from Related Links.), the watchdog is disabled and no other module uses CLKSRC

Bit 3 – CCS Core Clock Select

This bit selects between FRC oscillator clock and all other clock sources. The CCS bit must be written to logic ‘1’ to enable the mode selected with the CMM[2:0] bits. CMM[2:0] cannot be modified in this mode. If the CCS bit is written to logic ‘0’, the FRC oscillator clock is enabled and CMM[2:0] can be modified. If the CMM[2:0] bits in CMCR are not changing simultaneously, the CCS bit can only be set to ‘1’. After an external clock fail detection, the CCS bit is written to ‘0’.
Table 4-54. Core Clock Select Bit
CSSDescription
0The FRC oscillator is the active clock source and generates the input clock (CL). CMM[2:0] can be modified
1

The clock source selected by CMM[2:0] is active. Possible sources are: CLKEXT,CLKSRC,CLKXTO4, CLKXTO6,CLKADIV.

Modification of CMM[2:0] is not possible.

Bits 2:0 – CMM[2:0] Clock Management Mode

Table 4-55. Clock Source for System Clock Prescaler
Clock Source for System Clock Prescaler (CL)
CMM[2:0]CCS = 0CCS= 1
000FRCCLKSRC
001FRCCLKADIV
010FRCCLKEXT
011FRCCLKXTO6
100FRCCLKXTO4
101FRCCLKXTO4
110FRCCLKXTO4
111FRCCLKXTO4