4.9.4.4.2 CLKOD – Clock Output Divider

Name:	CLKOD
Offset:	0x0C3
Reset:	0x00

It can be modified only if the clock output is disabled (CLKOCR.CLKOEN = 0).


Bit	7	6	5	4	3	2	1	0
	CLKOD[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – CLKOD[7:0] Clock Output Divider

Divide the selected clock reference by this factor. The selected clock CLK_OS is passed to the CLK_OUT prescaler and the resulting divided clock is visible at the CLK_OUT pin if the output is enabled. See AVR Clock Systems in the System Clock and Clock Options from Related Links.

$f C L K_O U T = \frac{{f C L K}_{O S}}{2 x C L K O D} (46)$

CLKOD ∈ {0 .. 255}

If CLKOD = 0 is selected, the clock source is passed directly to the pin. The clock output frequency must never exceed the maximum specified frequency. For this reason, the divider must stay within the boundaries specified in the following table. For more details, refer to the ATA8210/ATA8215 UHF ASK/FSK Receiver Data Sheet (9344E), section 4.7, parameter number 15.90.


Selected CLK Source	Min. CLKOD	Max. CLKOD
CLK_SRC	0	255
CLK_FRC	1	255
CLK_XTO	3	255

Note: For more details, refer to the ATA8210/ATA8215 UHF ASK/FSK Receiver Data Sheet (9344E).