38.13.23 CxFIFOSTAy
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxFIFOSTAyT: Accesses the top byte FIFOSTAy[31:24]
- CxFIFOSTAyU: Accesses the upper byte FIFOSTAy[23:16]
- CxFIFOSTAyH: Accesses the high byte FIFOSTAy[15:8]
- CxFIFOSTAyL: Accesses the low byte FIFOSTAy[7:0]
- [y] denotes FIFO number, from 1 to 3.
- FIFOCI[4:0] gives a
zero-indexed value to the message in the FIFO. If the FIFO is four message
deep (FSIZE =
3), FIFOCIx will take on a value of0to3, depending on the state of the FIFO. - This bit is updated when a message completes (or aborts) or when the FIFO is reset.
- This bit is reset on any read of this register or when the TXQ is reset.
| Name: | CxFIFOSTAy |
| Offset: | 0x00 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIFOCI[4:0] | |||||||||
| Access | [R | [R | [R | [R | [R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXABT | TXLARB | TXERR | TXATIF | RXOVIF | TFERFFIF | TFHRFHIF | TFNRFNIF | ||
| Access | R | R | R | HS/C | HS/C | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 12:8 – FIFOCI[4:0] FIFO Message Index(3)
| Name | Description |
|---|---|
TXEN = 1 (FIFO configured as a
transmit buffer) |
A read of this register will return an index to the message that the FIFO will next attempt to transmit |
TXEN = 0 (FIFO configured as a
receive buffer) |
A read of this register will return an index to the message that the FIFO will use to save the next message |
Bit 7 – TXABT Message Aborted Status(5)
| Value | Description |
|---|---|
| 1 | Message was aborted |
| 0 | Message completed successfully |
Bit 6 – TXLARB Message Lost Arbitration Status(4)
| Value | Description |
|---|---|
| 1 | Message lost arbitration while being sent |
| 0 | Message did not lose arbitration while being sent |
Bit 5 – TXERR Error Detected During Transmission(4)
| Value | Description |
|---|---|
| 1 | A bus error occurred while the message was being sent |
| 0 | A bus error did not occur while the message was being sent |
Bit 4 – TXATIF Transmit Attempts Exhausted Interrupt Pending
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a
transmit buffer) |
Interrupt is pending |
| 0 | TXEN = 1 (FIFO configured as a
transmit buffer) |
Interrupt is not pending |
| x | TXEN = 0 (FIFO configured as a
receive buffer) |
Unused,
reads as ‘0’ |
Bit 3 – RXOVIF Receive FIFO Overflow Interrupt Flag
| Value | Name | Description |
|---|---|---|
| x | TXEN = 1 (FIFO configured as a
transmit buffer) |
Unused,
reads as ‘0’ |
| 1 | TXEN = 0 (FIFO configured as a
receive buffer) |
Overflow event has occurred |
| 0 | TXEN = 0 (FIFO configured as a
receive buffer) |
No overflow event occurred |
Bit 2 – TFERFFIF Transmit/Receive FIFO Empty/Full Interrupt Flag
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a
transmit buffer) |
FIFO is empty |
| 0 | TXEN = 1 (FIFO configured as a
transmit buffer) |
FIFO is not empty, at least one message is queued to be transmitted |
| 1 | TXEN = 0 (FIFO configured as a
receive buffer) |
FIFO is full |
| 0 | TXEN = 0 (FIFO configured as a
receive buffer) |
FIFO is not full |
Bit 1 – TFHRFHIF Transmit/Receive FIFO Half Empty/Half Full Interrupt Flag
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a
transmit buffer) |
FIFO is less than or equal to half full |
| 0 | TXEN = 1 (FIFO configured as a
transmit buffer) |
FIFO is greater than half full |
| 1 | TXEN = 0 (FIFO configured as a
receive buffer) |
FIFO is greater than or equal to half full |
| 0 | TXEN = 0 (FIFO configured as a
receive buffer) |
FIFO is less than half full |
Bit 0 – TFNRFNIF Transmit/Receive FIFO Not Full/Not Empty Interrupt Flag
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a
transmit buffer) |
FIFO is not full |
| 0 | TXEN = 1 (FIFO configured as a
transmit buffer) |
FIFO is full |
| 1 | TXEN = 0 (FIFO configured as a
receive buffer) |
FIFO is not empty, has at least one message |
| 0 | TXEN = 0 (FIFO configured as a
receive buffer) |
FIFO is empty |