11.13.25 Peripheral Interrupt Request Register 6

Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. SPI1IF is a read-only bit. To clear the interrupt condition, all bits in the SPI1INTF register must be cleared.
  3. SPI1TXIF and SPI1RXIF are read-only bits and cannot be set/cleared by software.
  4. I2C1EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C1ERR register must be cleared.
  5. I2C1IF is a read-only bit. To clear the interrupt condition, all bits in the I2C1PIR register must be cleared.
  6. I2C1TXIF and I2C1RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C1STAT1 must be set.
Name: PIR6
Offset: 0x4BC

Bit 76543210 
  SPI1IFSPI1TXIFSPI1RXIFI2C1EIFI2C1IFI2C1TXIFI2C1RXIF 
Access RRRRRRR 
Reset 0000000 

Bit 6 – SPI1IF  SPI1 Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 5 – SPI1TXIF  SPI1 Transmit Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 4 – SPI1RXIF  SPI1 Receive Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 3 – I2C1EIF  I2C1 Error Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – I2C1IF  I2C1 Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – I2C1TXIF  I2C1 Transmit Interrupt Flag(6)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – I2C1RXIF  I2C1 Receive Interrupt Flag(6)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. SPI1IF is a read-only bit. To clear the interrupt condition, all bits in the SPI1INTF register must be cleared. SPI1TXIF and SPI1RXIF are read-only bits and cannot be set/cleared by software. I2C1EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C1ERR register must be cleared. I2C1IF is a read-only bit. To clear the interrupt condition, all bits in the I2C1PIR register must be cleared. I2C1TXIF and I2C1RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C1STAT1 must be set.