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11.13.13 Peripheral Interrupt Enable
Register 6
Bit 7 6 5 4 3 2 1 0 SPI1IE SPI1TXIE SPI1RXIE I2C1EIE I2C1IE I2C1TXIE I2C1RXIE Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0
Bit 6 – SPI1IE SPI1 Interrupt
Enable
Value Description
1
Enabled
0
Disabled
Bit 5 – SPI1TXIE SPI1 Transmit
Interrupt Enable
Value Description
1
Enabled
0
Disabled
Bit 4 – SPI1RXIE SPI1 Receive
Interrupt Enable
Value Description
1
Enabled
0
Disabled
Bit 3 – I2C1EIE I2C1 Error
Interrupt Enable
Value Description
1
Enabled
0
Disabled
Bit 2 – I2C1IE I2C1 Interrupt
Enable
Value Description
1
Enabled
0
Disabled
Bit 1 – I2C1TXIE I2C1 Transmit
Interrupt Enable
Value Description
1
Enabled
0
Disabled
Bit 0 – I2C1RXIE I2C1 Receive
Interrupt Enable
Value Description
1
Enabled
0
Disabled
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