11.13.22 Peripheral Interrupt Request Register 3
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
| Name: | PIR3 |
| Offset: | 0x4B9 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMA2AIF | DMA2ORIF | DMA2DCNTIF | DMA2SCNTIF | DMA1AIF | DMA1ORIF | DMA1DCNTIF | DMA1SCNTIF | ||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – DMA2AIF DMA2 Abort Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 6 – DMA2ORIF DMA2 Overrun Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 5 – DMA2DCNTIF DMA2 Destination Count Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 4 – DMA2SCNTIF DMA2 Source Count Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 3 – DMA1AIF DMA1 Abort Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 2 – DMA1ORIF DMA1 Overrun Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 1 – DMA1DCNTIF DMA1 Destination Count Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 0 – DMA1SCNTIF DMA1 Source Count Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |