11.13.24 Peripheral Interrupt Request Register 5

Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. UxIF is a read-only bit. To clear the interrupt condition, all bits in the UxUIR register must be cleared.
  3. UxEIF is a read-only bit. To clear the interrupt condition, all bits in the UxERR register must be cleared.
  4. UxTXIF and UxRXIF are read-only bits and cannot be set/cleared by software.
Name: PIR5
Offset: 0x4BB

Bit 76543210 
 U2IFU2EIFU2TXIFU2RXIFU1IFU1EIFU1TXIFU1RXIF 
Access RRRRRRRR 
Reset 00000000 

Bit 7 – U2IF  UART2 Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 6 – U2EIF  UART2 Framing Error Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 5 – U2TXIF  UART2 Transmit Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 4 – U2RXIF  UART2 Receive Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 3 – U1IF  UART1 Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – U1EIF  UART1 Framing Error Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – U1TXIF  UART1 Transmit Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – U1RXIF  UART1 Receive Interrupt Flag(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. UxIF is a read-only bit. To clear the interrupt condition, all bits in the UxUIR register must be cleared. UxEIF is a read-only bit. To clear the interrupt condition, all bits in the UxERR register must be cleared. UxTXIF and UxRXIF are read-only bits and cannot be set/cleared by software.