14.2.2.1 I²C Byte Transfer

A typical I²C 8-bit data transfer cycle is shown in the following figure. A start condition is signaled when the SDA line goes Low while the SCL line is High. After a start condition, the master transmits the 7-bit slave address followed by a direction bit, which is decoded and acknowledged (ACK) by the slave. Following the address phase, multiple bytes can be transferred with an ACK for each byte. The end of the transaction is signaled by a stop condition. The stop condition is signaled by the SDA line asserted High while the SCL line is High.

When the I²C peripheral is in a receiver (Master or Slave) mode, it might acknowledge or ignore the data sent by the transmitter. The I²C peripheral must send a no-acknowledge (NACK) bit during the acknowledge cycle on the bus to disable the data transfer by signaling the stop condition.