14.2.3.2.1 Baud Rate Clock

BCLK is a pulse-for-transmission speed control signal and is internally synchronized with the clock input. BCLK is used to set the serial clock frequency from a clock sourced within the FPGA fabric when the CR[2:0] bits in the Control register are set to 0b111(0x7). Otherwise, either APB_0_CLK or APB_1_CLK is used to determine the serial clock frequency. The actual non-stretched serial bus clock frequency can be calculated based on the settings in the CR[2:0] fields of the Control register and the frequencies of APB_0_CLK or APB_1_CLK and BCLK. See 14.4.1 Control Register for more information on bit settings.