11.3.2 EDAC CAN Configuration

In radiation prone environments, storage elements such as RAMs and FIFOs are susceptible to transient errors caused by heavy ions. Errors can be detected and corrected by employing EDAC. The EDAC controller implemented in SmartFusion 2 device supports SECDED. The CAN controller internal RAMs are one of the RAMs that are protected by EDAC within SmartFusion 2 devices.

The values entered in the configurator are exported into the programming files to program the Flash bits that control this functionality. The Flash bits are loaded in the system registers at power-up (or when the DEVRST_N external pad is asserted or deasserted).

To configure (enable/disable) EDAC for the CAN controller, the SECDED configurator is used within the MSS configurator in Libero SoC.

Figure 11-8. Enabling EDAC for the CAN from the SECDED Configurator
  • Expose EDAC_ERROR Bus - Use to expose the EDAC_ERROR bus signal to the FPGA fabric, to be used by the design.
  • Enable EDAC - Use to enable EDAC functionality for the CAN controller.
  • Enable EDAC Interrupt(s) - Use to enable the EDAC interrupts for the CAN controller. Interrupts for 1-bit error and 2-bit error or both can be enabled, as shown in the preceding figure. For more information on the SECDED configurator options and ports descriptions, see MSS EDAC Configuration User Guide.
Important: The MSS CAN does not support full behavioral simulation models. For more information, see SmartFusion2 MSS BFM Simulation User Guide.