20.3 CoreResetP Soft Reset Controller

The following Reset sub-systems in SmartFusion 2 devices that must be sequenced properly for the overall system to function correctly:

• Chip Boot (System Controller)
• Fabric
• MSS, Cortex-M3 processor
• FIC sub-systems (MSS to Fabric and Fabric to MSS)
• Peripherals: MDDR, FDDR, and SERDESIF

CoreResetP Soft Reset Controller gathers various reset signals from the system controller, MSS, and FPGA fabric and, generates new synchronized reset signals to handle the sequencing of reset signals of various subsystems in SmartFusion 2 devices. CoreResetP helps manage the following:

• The FIC sub-systems resets: Both MSS and FPGA fabric should be out of reset to establish the communication between them. CoreResetP generates the MSS_READY signal, which indicates that both MSS and FPGA fabric are out of reset and ready for communication.
• The Peripherals Initialization: It generates resets signals to initialize MDDR, FDDR, and SERDESIF peripheral blocks.
• The Peripherals Reconfiguration: Individual reset controls via CoreConfigP Soft core.
• The PCIe L2/P2 (in-band) and PRST# (out-band) low power modes for all devices, except M2S090.