20.5 SYSREG Control Registers
The description of registers are located in the SYSREG section of the user's guide and are listed in the following table. Refer to the System Register Block for a detailed description of each register and bit.
| Register Name | Register Type | Flash Write Protect | Reset Source | Description |
|---|---|---|---|---|
| GPIO System Reset Control Register | RW-P | Register | PORESET_N | Configures the GPIO system reset |
| Software Reset Control Register | RW-P | Bit | SYSRESET_N | Generates the software control resets to the MSS peripherals |
| Reset Source Control Register | RW | — | — | Reset source control register. The source of Cortex-M3 processor reset is captured in this register. The reset values are mentioned in the bit definitions. |
| MDDR Configuration Register | RW-P | Register | PORESET_N | MDDR configuration register |
| Watchdog Configuration Register | RW-P | Register | PORESET_N | It configures Watchdog timer |
| MSS DDR Fabric Alignment Clock Controller (FACC) Configuration Register 1 | RW-P | Field | CC_RESET_N | MSS DDR Bridge fabric alignment clock controller 1 configuration register |