20.5 SYSREG Control Registers

The description of registers are located in the SYSREG section of the user's guide and are listed in the following table. Refer to the 21 System Register Block for a detailed description of each register and bit.

Table 20-4. Switch Register Map
Register Name Register Type Flash Write Protect Reset Source Description
21.5.23 GPIO System Reset Control Register RW-P Register PORESET_N Configures the GPIO system reset
21.5.19 Software Reset Control Register RW-P Bit SYSRESET_N Generates the software control resets to the MSS peripherals
21.5.44 Reset Source Control Register RW Reset source control register. The source of Cortex-M3 processor reset is captured in this register. The reset values are mentioned in the bit definitions.
21.5.25 MDDR Configuration Register RW-P Register PORESET_N MDDR configuration register
21.5.28 Watchdog Configuration Register RW-P Register PORESET_N It configures Watchdog timer
21.5.38 MSS DDR Fabric Alignment Clock Controller (FACC) Configuration Register 1 RW-P Field CC_RESET_N MSS DDR Bridge fabric alignment clock controller 1 configuration register