16.1 Features

The COMM_BLK peripheral includes the following features:

• Bi-directional byte-wide message path
• Supports serial data rate up to 50 Mbytes/sec
• Asynchronous clock support
  • Data clock (50 MHz RC oscillator) is different from advanced peripheral bus (APB) clock
• 8 byte transmit FIFO
• 8 byte receive FIFO
• Flow control
  • RX to TX channels between Microcontroller Subsystem (MSS) COMM_BLK and system controller COMM_BLK
  • MSS COMM_BLK to Peripheral Direct Memory Access (PDMA) channel
• Frame and/or command marker
  • 9th bit used as frame start or command marker
  • Allows command and data sequences to be distinguished
  • Allows incomplete sequences to be detected
  • Separate command interrupt received with programmable match logic
• Allows WORD transfers into FIFO in a single APB cycle
• Interrupts
  • RX FIFO non-empty
  • TX FIFO non-full
  • TX overflow
  • RX Underflow

The following figure depicts the connectivity of COMM_BLK to the Advanced High-Performance Bus (AHB) matrix.