3.1 Features

  • 8 KB of cache size
  • Four-way set associativity: Cache Controller has a four-way set associative cache subsystem with 32 byte cache lines organized as 64 sets of 4 cache lines, with a total of 256 locations.
  • Cache line size is 32 bytes, fixed irrespective of DDR burst.
  • Least recently used (LRU) cache line replacement policy.
  • Fill mechanism: Full cache line refill and critical word first.
  • The Cortex-M3 processor can write to Cache Memory through the System bus (SBUS).
  • Zero wait state in case of a hit (instruction in Cache Memory) and can run up to the maximum system frequency.
  • Supports Cache locked mode
  • Cache is constructed of latches

The following figure depicts the connectivity of the Cache Controller in a SmartFusion 2 device.

Figure 3-1. Cache Controller Interfaces to Cortex-M3 Processor, AHB Bus Matrix, and MDDR Bridge