3.3 How to Use Cache Controller

Cache Controller can be configured statically by using the Libero design software. The following figure shows the Cache Controller enable option, cache region size selection.

Figure 3-7. MSS Configurator with Cache Controller Configuration Options

The following figure shows how to select the main memory from memory blocks eNVM, eSRAM, and DDR SDRAM.

Figure 3-8. MSS Configurator with Remapping Options for eNVM, eSRAM, and MDDR

The selection of the main memory for the Cache Controller can also be made using the system builder flow of the Libero SoC software. This procedure is explained in the following figure.

Figure 3-9. System Builder with Remapping Options for eNVM, eSRAM, and MDDR

Cache Controller configurations like enable/disable, selecting the main memory, and Cache Locked mode can also be performed using the firmware/application code with the register settings provided in the 3.3.1 System Registers Used for Cache Operations.

See the following application notes for more details on the Cache Controller configurations:

Important: Create or modify the linker scripts/linker settings of the application in such a way that all read and write data sections are in non-cacheable memory regions or accessed through the system bus address space. This note has to be strictly followed if eSRAM or DDR SDRAM are selected as the main memory for the cache.