6.2.1 Design Flow

The following steps are used to configure the AHB bus matrix in the application:

  1. Configure the AHB bus matrix by using the MSS configurator in the application, as shown in the following figure.
    Figure 6-18. AHB Bus Matrix in Libero® SoC Design MSS Configurator
  2. Click AHB Bus Matrix to configure it. The AHB Bus Matrix configuration window is shown in the following figure.
    • The AHB bus matrix provides support to remap eNVM, eSRAM, and DDR memory regions to location 0x000000000 of the Cortex-M3 ID code space. It also provides an option to remap eNVM for a Soft Processor eNVM Remap. To enable remapping for eNVM, eSRAM, and DDR select appropriate option from remapping section of AHB Bus Matrix configurator.
      Figure 6-19. AHB Bus Matrix Configuration Window
    • Enter the weight values for the masters in arbitration section, to configure the programmable weight registers MASTER_WEIGHT0_CR and MASTER_WEIGHT1_CR. These are located in the SYSREG block with the required weight values. The weight values range is from 1 to 32.
    • Enter the maximum latency values for the fixed priority masters to configure ESRAM_MAX_LAT registers that are located in the SYSREG block. 
This decides the peak wait time for a fixed priority master arbitrating for eSRAM access while the WRR master is accessing the slave. Slave maximum latency can be configured from 1 to 8 clock cycles (8 by default).
      Important: ESRAM_MAX_LAT is only supported for fixed priority masters addressing eSRAM slaves. It has no effect on WRR masters.
  3. Generate the component by clicking Generate Component or by selecting SmartDesign > Generate Component.

    For more information on generation of the component, see the latest SmartDesign User Guide on 
Libero SoC User Guide page.

  4. Click Generate Bitstream under Program Design to complete *.fdb file generation.
    Important: The MSS AHB Bus Matrix supports full behavioral simulation models. For more information, see SmartFusion2 MSS BFM Simulation User Guide.