12.1 Features

SmartFusion 2 MMUART peripherals support the following features:

  • Asynchronous and synchronous operations
  • Full programmable serial interface characteristics
    • Data width is programmable to 5, 6, 7, or 8 bits
    • Even, odd, or no-parity bit generation/detection
    • 1, 1½, and 2 stop bit generation
  • 9-bit address flag capability used for multi-drop addressing topologies
  • Separate transmit (Tx) and receive (Rx) FIFOs to reduce processor interrupt service loading
  • Single-wire half-duplex mode in which Tx pad can be used for bi-directional data transfer
  • Local Interconnect Network (LIN) header detection and auto baud rate calculation
  • Communication with ISO 7816 smart cards
  • Fractional baud rate capability
  • Return to Zero Inverted (RZI) mod/demod blocks that allow Infrared Data Association (IrDA) and Serial Infrared (SIR) communications
  • The Most Significant Bit (MSB) or the Least Significant Bit (LSB) as the first bit while sending or receiving data

The following figure shows the MMUART peripherals within the MSS. The MMUART peripherals are interfaced to the AHB bus matrix through APB interfaces (APB_0 and APB_1).

Figure 12-1. MSS Showing MMUART Peripherals