12.4 MMUART Register Map

The MMUART_0 base address resides at 0x40000000 and extends to address 0x40000FFF in the Cortex-M3 processor memory map. The MMUART_1 base address resides at 0x40010000 and extends to address 0x40010FFF in the Cortex-M3 processor memory map. The following table summarizes the control and status registers for MMUART _0 and MMUART_1.

Table 12-4. MMUART Register Definitions
Register Name	Divisor Latch Access Bit (DLAB)¹	Address Offset	Read/Write	Reset Value	Description
Table 12-5	0	0x0	R	N/A	Receiver buffer register
Table 12-6	0	0x0	W	N/A	Transmit holding register
Table 12-8	1	0x0	R/W	0x01	Divisor latch (LSB)
Table 12-9	1	0x04	R/W	0	Divisor latch (MSB)
Table 12-10	N/A	0x3C	R/W	0	Fractional divisor register
Table 12-12	0	0x04	R/W	0	Interrupt enable register
Table 12-13	N/A	0x24	R/W	0	Multi-mode interrupt enable register
Table 12-14	N/A	0x08	R	0x01	Interrupt identification register
Table 12-16	N/A	0x28	Clear on R	0	Multi-mode interrupt identification register
Table 12-7	N/A	0x08	W	0	FIFO control register
Table 12-17	N/A	0x0C	R/W	0	Line control register
Table 12-18	N/A	0x10	R/W	0	Modem control register
Table 12-19	N/A	0x14	R	0x60	Line status register
Table 12-20	N/A	0x18	R	0	Modem status register
Table 12-21	N/A	0x1C	R/W	0	Scratch register
Table 12-22	N/A	0x30	R/W	0	Multi-mode control register0
Table 12-23	N/A	0x34	R/W	0	Multi-mode control register1
Table 12-24	N/A	0x38	R/W	0	Multi-mode control register2
Table 12-25	N/A	0x44	R/W	0	Glitch filter register
Table 12-26	N/A	0x48	R/W	0	Transmitter time guard register
Table 12-27	N/A	0x4C	R/W	0	Receiver time-out register
Table 12-28	N/A	0x50	R/W	0	Address register

Note:

DLAB is the MSB of the line control register (LCR bit 7).

The following tables provide the register bit descriptions in detail.