27.4.3.2.4 Input Capture Buffer

The Input Capture FIFO buffer is up to four levels deep, depending on the Capture mode selected. For 16-bit timer captures, there are four levels in the FIFO (16-bit wide); for 32-bit timer captures, there are two levels (32-bit wide). The number of capture events required to generate a CPU interrupt can be selected by the user.

There are two status flags that provide status on the FIFO buffer. The ICBNE status bit (CCPxSTAT[0]) indicates that at least one capture event has occurred. The ICOV status bit (CCPxSTAT[1]) indicates that there have been more events than the buffer’s current depth (four in 16-bit mode, two in 32-bit mode). These status flags operate the same for 16-bit capture operations and 32-bit capture operations.

While the CCP module is in Reset or not in Capture mode:
  • The ICOV status flag is cleared
  • The ICBNE status flag is cleared
  • The FIFO is marked as empty
  • A read of the FIFO buffer will return ‘0’

The ICBNE status flag is set on the first capture event and remains set until all capture events have been read from the FIFO. For example, if three capture events have occurred, then three reads of the Capture FIFO buffer are required before the ICBNE flag will be cleared. Each read of the FIFO buffer will allow the remaining word(s) to move to the next available top location of the FIFO.

In the event that the FIFO buffer is full with capture events and another capture event occurs prior to a read of the FIFO, an Overflow condition will occur and the ICOV bit becomes set. In addition, the capture event which caused the Overflow is not recorded, and subsequent capture events will not be placed into the FIFO until the Overflow condition is cleared by completely emptying the FIFO.

Overflow conditions cannot occur when the module is not in an Input Capture mode or when Edge Detect mode is enabled (MOD[3:0] = 0000).

Clearing of the Overflow condition can be accomplished in one of the following ways:
  1. Disable the module by clearing the CCPON bit.
  2. Read the Input Capture buffer until ICBNE = 0 (twice for 32-bit captures, four times for 16-bit captures).
  3. Clear the ICOV bit in software. This effectively discards all previously stored data in the FIFO by resetting the data pointers to the beginning of the FIFO buffer. Clearing the ICOV in software also causes the ICBNE bit to be cleared automatically.
  4. Perform a device Reset.

Upon clearing the Overflow condition, the ICBNE status flag is cleared, and to resume the Capture mode the user software must clear the ICOV status flag. If the module is disabled, and then re-enabled in Input Capture mode later, the FIFO buffer contents will be undefined and a read will yield indeterminate results.

In the event that a FIFO read is performed after the last read and no new capture event has been received, the FIFO read and write pointers will be pointing to the first buffer location of the FIFO. A read of the FIFO will return the value held in the first buffer location.

The FIFO pointer is adjusted whenever the most significant word of the buffer result is read by the CPU. This allows the results of a 32-bit Input Capture to be read by the 16-bit CPU.