27.4.3.2 Capture Event Modes
The module can capture a timer value on any of the following ICx pin transitions:
- Every rising edge (MOD[3:0] =
0001) - Every falling edge (MOD[3:0] =
0010) - Every rising and falling edge (MOD[3:0] =
0000,0011)
Since the Input Capture pin is sampled on the falling edge of the timer clock; the capture pulse width must be greater than the timer clock period, plus some margin.
Because of internal synchronization requirements, the timer value captured will be up to 1.5 CCP clock cycles after the time of the actual capture edge event, as shown in Figure 27-6.