6.4.2.1 Cache Control Register

Note:
  1. After being set, this bit will be cleared by hardware after the cache and ISB invalidations are completed. Any automatic invalidation will also result in this bit being cleared.
  2. This setting is useful when programming non-program data into Flash (emulated EEPROM).
Table 6-26. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: CHECON
Offset: 0x1E60

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 ON   CHEINVCHECOH   
Access R/WR/S/HCR/W 
Reset 111 
Bit 76543210 
        FLTINJ 
Access R/S/HC 
Reset 1 

Bit 15 – ON Cache ON bit

ValueDescription
1Cache and all ISB slices are enabled
0All cache lines and ISB buffers except for the first buffer slice are invalidated. ISB operates with one buffer slice, two deep buffer (basic prefetch mode).

Bit 11 – CHEINV  Manual Invalidate Control bit(1)

ValueDescription
1Force invalidation of all cache and ISB lines
0Invalidation of Instruction Cache and ISBs occurs according to CHECOH bit

Bit 10 – CHECOH  Cache Coherency Control bit(2)

ValueDescription
1Invalidate cache upon a Flash programming event
0Do not invalidate cache on a Flash programming event

Bit 0 – FLTINJ Fault Inject Control bit

ValueDescription
1Parity Fault injection enabled for one-time event; cache line will be invalidated and flushed when access occurs and upbs_event[1] will be asserted to indicate an integrity error to the system.
0Parity Fault injection disabled