6.4.2.2 Cache Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CHESTAT |
| Offset: | 0x1E64 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RD | PAR | ||||||||
| Access | R/W | R/S/HC | |||||||
| Reset | 1 | 1 |
Bit 1 – RD Read Error Status bit
| Value | Description |
|---|---|
| 1 | A read error event has occurred; the CPU has fetched a word from the ISB with a security error |
| 0 | No read error event has occurred |
Bit 0 – PAR Cache Parity Error Status bit
| Value | Description |
|---|---|
| 1 | A parity error event has occurred; the CPU has fetched a word from the cache with a parity error |
| 0 | No parity error event has occurred |