6.4.2.3 Cache Fault Injection Register

Table 6-28. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	CHEFLTINJ
Offset:	0x1E68


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	FLTPTR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	1

Bits 7:0 – FLTPTR[7:0] Fault Injection Pointer bits

Value	Description
255-129	No effect
128	Cache Data Line Parity bit
127	Bit 127 of cache data line
...
1	Bit 1 of cache data line
0	Bit 0 of cache data line

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.