27.4.7.5.2 CCPxTMR Writes with Asynchronous Clock Source

When an asynchronous clock source is used, writes to CCPxTMR are buffered and the write progress is indicated using the TMRHWIP (CCPxSTAT[19]) and TMRLWIP (CCPxSTAT[18]) status bits. The write to the CCPxTMR register is complete when the appropriate WIP status bit is cleared by hardware. Another write can be safely performed after the WIP is cleared.

Note: These status bits are also affected when the clock is synchronous. However, it is not necessary to monitor these bits since the write will occur on the next system clock cycle.

The timer WIP bits are set as follows:

In Dual 16-Bit Timer mode, TMRHWIP is set upon a write that includes the highest byte of CCPxTMRH. TMRLWIP is set upon a write that includes the highest byte of CCPxTMRL.
In modes that use a single 16-bit timer, TMRLWIP is set upon a write that includes the highest byte of CCPxTMRL.
In modes that use a 32-bit timer, TMRLWIP and TMRHWIP are set upon a write that includes the highest byte of CCPxTMRH.

User software should not perform any writes to CCPxTMR while the appropriate WIP bit is set; otherwise, an unexpected timer value may result.

Note: The TMRHWIP and TMRLWIP bits get set automatically when the CCPON bit is set. This ensures any modifications to the CCPxTMR register while the macro is off will take effect. The user may monitor the WIP bits after the CCPON bit is set to determine when the CCPxTMR contents have been updated and the time base has begun counting.