27.4.3.4.1 Input Capture Signal Gating

The Input Capture source can optionally be gated by software or hardware to allow windowed capture measurements. This feature provides noise immunity in sensing applications.

The CDIS bit (CCPxSTAT[2]) provides the status of the input signal gating function. When the CDIS bit is cleared, capture events generated by the edge detect logic are allowed. When the CDIS bit is set, events from the edge detect logic are inhibited.

The time base gating logic is used for Input Capture signal gating (see Gating Logic for more information). The ASDG[7:0] control bits (CCPxCON2[7:0]) select one or more input sources that are used to clear the CDIS status/control bit. The SSDG bit (CCPxCON2[12]) may also be used to manually gate Input Capture signals in software.

The behavior of the ASDGx sources and the SSDG bit depends on the Gating Source mode, which is selected using the ICGSM[1:0] control bits (CCPxCON2[23:22]). Three different options are available:
  • When ICGSM[1:0] = 00, gating is level-sensitive. A low input level from the gating source disables subsequent capture events and the CDIS bit will be set to reflect this. A high input level enables subsequent capture events and the CDIS bit will be cleared to reflect this.
  • When ICGSM[1:0] = 01, gating occurs with a rising edge of the gating source; the CDIS bit is cleared, disabling subsequent capture events. This is a One-Shot mode; subsequent edges from the gating source will have no effect.
  • When ICGSM[1:0] = 10, gating occurs on the falling edge of the gating source; the CDIS bit is set, enabling subsequent capture events. This is a One-Shot mode; subsequent edges from the gating source will have no effect.
When ICGSM[1:0] = 01 or 10, the input capture gating logic operates in a One-Shot mode as described above. The user may arm the gating logic after a gating event by writing a ‘1’ to the ICGARM (CCPxSTAT[10]) bit. This write to ICGARM has the effect of resetting the gate signal edge detection logic and also resets the CDIS status bit to the appropriate value. User software can determine the state of the one-shot logic by reading the CDIS status bit:
  • When ICGSM[1:0] = 01 and a ‘1’ is written to ICGARM, the gate signal edge detection logic is armed to look for a rising edge and the CDIS bit is set to disable input capture events until the rising edge occurs on the gate signal.
  • When ICGSM[1:0] = 10 and a ‘1’ is written to ICGARM, the gate signal edge detection logic is armed to look for a falling edge and the CDIS bit is cleared to enable input capture events until the next falling edge occurs on the gate signal.

Figure 27-8 shows the timing for gated capture events. Input events are sampled on the falling edge of the clock source. The example assumes that the Input Capture module is configured to capture every rising and falling edge (MOD[3:0] = 0011).

In the One-Shot modes, the edge detect logic is set to look for the appropriate edge event; the CDIS bit remains set or clear (depending on the mode) until that type of event occurs. The user may re-arm the gating logic after a gating event by rewriting ICGSM[1:0]. This act of writing to these bits (even if the same value) resets the gate signal edge detection logic and also resets the CDIS status bit to the appropriate value.

To use Input Capture gating:
  1. Select and configure the gating source.
  2. Enable the appropriate gating signal source(s) using the ASDG[7:0] bits; alternatively, set or clear the SSDG bit during the event for software only control.
  3. Select the Gating mode using ICGSM[1:0].
  4. Configure the module for the desired Input Capture mode and input source using the MOD[3:0] and ICS[2:0] control bits. The module is now armed for a gate event.
  5. The next valid rising or falling input signal edge (depending on Capture mode) after CDIS is cleared will trigger a capture event.
Figure 27-8. Gated Input Capture Examples