32.6.8 Channel n Control

Important: For PIC32CM LS00/LS60 Non-Secure accesses, read and write accesses (RW*) are allowed only if the security attribution for the corresponding channel (CHANNELn) is set as Non-Secured in the NONSECCHAN register.

This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.

Name:	CHANNELn
Offset:	0x20 + n*0x08 [n=0..11]
Reset:	0x00008000 (CHANNEL0-7), 0x00000000 (CHANNEL8-11)
Property:	PAC Write-Protection, Mix-Secure


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	ONDEMAND	RUNSTDBY			EDGSEL[1:0]		PATH[1:0]
Access	RW/RW*/RW	RW/RW*/RW			RW/RW*/RW	RW/RW*/RW	RW/RW*/RW	RW/RW*/RW
Reset	x	0			0	0	0	0


Bit	7	6	5	4	3	2	1	0
		EVGEN[6:0]
Access		RW/RW*/RW	RW/RW*/RW	RW/RW*/RW	RW/RW*/RW	RW/RW*/RW	RW/RW*/RW	RW/RW*/RW
Reset		0	0	0	0	0	0	0

Bit 15 – ONDEMAND Generic Clock On Demand

This bit is used to determine whether the generic clock is requested.

This bit has no effect for channels when asynchronous path is selected or for channels with asynchronous support only.

This bit is always read zero for channels with asynchronous support only.

Value	Description
0	Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled.
1	Generic clock is requested on demand while an event is handled

Bit 14 – RUNSTDBY Run in Standby

This bit is used to define the behavior during Standby Sleep mode, for a resynchronized channel.

This bit has no effect for channels when asynchronous path is selected or for channels with asynchronous support only.

This bit is always read zero for channels with asynchronous support only.

Value	Description
0	The channel is disabled in Standby Sleep mode.
1	The channel is not stopped in Standby Sleep mode and depends on the CHANNEL.ONDEMAND bit.

Bits 11:10 – EDGSEL[1:0] Edge Detection Selection

These bits set the type of edge detection to be used on the channel.

These bits must be written to zero when using the asynchronous path.

Value	Name	Description
0x0	NO_EVT_OUTPUT	No event output when using the resynchronized or synchronous path
0x1	RISING_EDGE	Event detection only on the rising edge of the signal from the event generator
0x2	FALLING_EDGE	Event detection only on the falling edge of the signal from the event generator
0x3	BOTH_EDGES	Event detection on rising and falling edges of the signal from the event generator

Bits 9:8 – PATH[1:0] Path Selection

These bits are used to choose which path will be used by the selected channel.

Note: The path choice can be limited by the channel source, see the table in USERm.

Important: Only EVSYS channel 0 to 7 can be configured as synchronous or resynchronized.

Value	Name	Description
0x0	SYNCHRONOUS	Synchronous path
0x1	RESYNCHRONIZED	Resynchronized path
0x2	ASYNCHRONOUS	Asynchronous path
Other	-	Reserved

Bits 6:0 – EVGEN[6:0] Event Generator Selection

These bits are used to choose the event generator to connect to the selected channel.

Table 32-3. Event Generators (PIC32CM2532 and PIC32CM5164 devices)
Value	Event Generator	Description
0 (0x00)	NONE	No event generator selected
1 (0x01)	CFD	XOSC clock failure detection (OSCCTRL)
2 (0x02)	CFD	XOSC32K clock failure detection (OSC32KCTRL)
3 (0x03)	BOD33DET	SUPC BOD33 detection
4-11 (0x04-0x0B)	PER0-7	RTC period
4 (0x04)	ALARM0	RTC alarm (Clock/Calendar mode)
12-13 (0x0C-0x0D)	CMP0-1	RTC comparison (COUNT16 and COUNT32 modes)
14 (0x0E)	TAMPER	RTC tamper detection
15 (0x0F)	OVF	RTC overflow
16 (0x10)	PERD	RTC periodic interval daily
17-32 (0x11-0x20)	EXTINT0-15	EIC external interrupt
33- 40 (0x21-0x28)	CH0-7	DMAC channel
41 (0x29)	OVF	TC0 overflow
42-43 (0x2A-0x2B)	MC0-1	TC0 match/compare
44 (0x2C)	OVF	TC1 overflow
45-46 (0x2D-0x2E)	MC0-1	TC1 match/compare
47 (0x2F)	OVF	TC2 overflow
48-49 (0x30-0x31)	MC0-1	TC2 match/compare
50 (0x32)	TRG	TCC0 trigger
51 (0x33)	CNT	TCC0 counter
52-55 (0x34-0x37)	MC0-3	TCC0 match/compare
56 (0x38)	OVF	TCC0 overflow/underflow
57 (0x39)	TRG	TCC1 trigger
58 (0x3A)	CNT	TCC1 counter
59-50 (0x3B-0x3C)	MC0-1	TCC1 match/compare
61 (0x3D)	OVF	TCC1 overflow/underflow
62 (0x3E)	TRG	TCC2 trigger
63 (0x3F)	CNT	TCC2 counter
64-65 (0x40-0x41)	MC0-1	TCC2 match/compare
66 (0x42)	OVF	TCC2 overflow/underflow
67 (0x43)	TRG	TCC3 trigger
68 (0x44)	CNT	TCC3 counter
69-72 (0x45-0x48)	MC0-3	TCC3 match/compare
73 (0x49)	OVF	TCC3 overflow/underflow
74 (0x4A)	RESRDY	ADC resolution ready
75 (0x4B)	WINMON	ADC window monitor
76-79 (0x4C-0x4F)	COMP0-3	AC comparator
80-81 (0x50-0x51)	WIN0-1	AC window
82-83 (0x52-0x53)	EMPTY0-1	DAC empty
84 (0x54)	EOC	PTC end of conversion
85 (0x55)	WCOMP	PTC window comparator
86 (0x56)	DATARDY	TRNG Data Ready
87-90 (0x57-0x5A)	LUT0-3	CCL LUT output
91 (0x5B)	ERR	PAC access error

Table 32-4. Event Generators (PIC32CM1216 devices)
Value	Event Generator	Description
0 (0x00)	NONE	No event generator selected
1 (0x01)	CFD	XOSC clock failure detection
1 (0x01)	CFD	(OSCCTRL)
2 (0x02)	CFD	XOSC32K clock failure detection
2 (0x02)	CFD	(OSC32KCTRL)
3 (0x03)	BOD33DET	SUPC BOD33 detection
4-11 (0x04-0x0B)	PER0-7	RTC period
4 (0x04)	ALARM0	RTC alarm (Clock/Calendar mode)
12-13 (0x0C-0x0D)	CMP0-1	RTC comparison (COUNT16 and
12-13 (0x0C-0x0D)	CMP0-1	COUNT32 modes)
14 (0x0E)	TAMPER	RTC tamper detection
15 (0x0F)	OVF	RTC overflow
16 (0x10)	PERD	RTC periodic interval daily
17-24 (0x11-0x18)	EXTINT0-7	EIC external interrupt
25-32 (0x19-0x20)	CH0-7	DMAC channel
33 (0x21)	OVF	TC0 overflow
34-35 (0x22-0x23)	MC0-1	TC0 match/compare
36 (0x24)	OVF	TC1 overflow
37-38 (0x25-0x26)	MC0-1	TC1 match/compare
39 (0x27)	OVF	TC2 overflow
40-41 (0x28-0x29)	MC0-1	TC2 match/compare
42 (0x2A)	RESRDY	ADC resolution ready
43 (0x2B)	WINMON	ADC window monitor
44-45 (0x2C-0x2D)	COMP0-1	AC comparator
46 (0x2E)	WIN0	AC window
47-48 (0x2F-0x30)	EMPTY0-1	DAC empty
49 (0x31)	EOC	PTC end of conversion
50 (0x32)	WCOMP	PTC window comparator
51 (0x33)	DATARDY	TRNG Data Ready
52-53 (0x34-0x35)	LUT0-1	CCL LUT output
54 (0x36)	ERR	PAC access error