35.7.5 MPDDRC Timing Parameter 1 Register

This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.

Name: MPDDRC_TPR1
Offset: 0x10
Reset: 0x03C80808
Property: Read/Write

Bit 3130292827262524 
     TXP[3:0] 
Access R/WR/WR/WR/W 
Reset 0011 
Bit 2322212019181716 
 TXSRD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11001000 
Bit 15141312111098 
 TXSNR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00001000 
Bit 76543210 
  TRFC[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0001000 

Bits 27:24 – TXP[3:0] Exit Power-down Delay to First Command

This field defines the delay between CKE set high and a valid command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.

Bits 23:16 – TXSRD[7:0] Exit Self-refresh Delay to Read Command

This field defines the delay between CKE set high and a Read command in number of DDRCK clock cycles. The number of cycles is between 0 and 255.

This field is found only in DDR2-SDRAM and DDR3-SDRAM devices.

In case of DDR3-SDRAM, this field is equivalent to tXSDLL. In DLL Off mode, this timing is not used. The field must be set to 0.

Bits 15:8 – TXSNR[7:0] Exit Self-refresh Delay to Non-Read Command

This field defines the delay between CKE set high and a Non Read command in number of DDRCK clock cycles. The number of cycles is between 0 and 255. This field is used by the DDR-SDRAM devices. In case of low-power DDR-SDRAM, this field is equivalent to tXSR. In case of DDR3-SDRAM, this field is equivalent to tXS.

Bits 6:0 – TRFC[6:0] Row Refresh Cycle

This field defines the delay between a Refresh command or a Refresh and Activate command in number of DDRCK clock cycles. The number of cycles is between 0 and 127.

In case of low-power DDR2-SDRAM and low-power DDR3-SDRAM, this field is equivalent to tRFCab. If the user enables the function “Refresh Per Bank” (see “REF_PB: Refresh Per Bank”), this field is equivalent to tRFCpb.