35.7.11 MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register
| Name: | MPDDRC_LPDDR2_LPDDR3_DDR3_TIM_CAL |
| Offset: | 0x30 |
| Reset: | 0x00000006 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RZQI[1:0] | |||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ZQCS[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | |
Bits 17:16 – RZQI[1:0] Built-in Self-Test for RZQ Information
Indicates whether the device has detected a resistor connection to the ZQ pin.
This mode is unique to low-power DDR3-SDRAM devices.
| Value | Name | Description |
|---|---|---|
| 0 | RZQ_NOT_SUPPORTED | RZQ self test not supported |
| 1 | ZQ_VDDCA_FLOAT | The ZQ pin can be connected to VDDCA or left floating. |
| 2 | ZQ_SHORTED_GROUND | The ZQ pin can be shorted to ground. |
| 3 | ZQ_SELF_TEST_OK | ZQ pin self test complete; no error condition detected |
Bits 7:0 – ZQCS[7:0] ZQ Calibration Short
Defines the delay between the ZQ Calibration command and any valid command in number of DDRCK clock cycles.
The number of cycles is between 0 and 255. This field applies to LPDDR2, LPDDR3 and DDR3 devices.