35.7.22 MPDDRC Read Data Path Register

Name: MPDDRC_RD_DATA_PATH
Offset: 0x5C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       SHIFT_SAMPLING[1:0] 
Access R/WR/W 
Reset 00 

Bits 1:0 – SHIFT_SAMPLING[1:0] Shift Sampling Point of Data

Shifts the sampling point of data coming from the memory device. The higher the memory device clock frequency, the higher the SHIFT_SAMPLING value. Refer to the section "Electrical Characteristics".

In the case of DDR3-SDRAM devices, the field SHIFT_SAMPLING must be set to 2, and the field CAS must be set to 5. See “CAS: CAS Latency” in MPDDRC_CR.

ValueNameDescription
0 NO_SHIFT Initial sampling point.
1 SHIFT_ONE_CYCLE Sampling point is shifted by one cycle.
2 SHIFT_TWO_CYCLES Sampling point is shifted by two cycles.
3 SHIFT_THREE_CYCLES Sampling point is shifted by three cycles, unique for LPDDR2, DDR3 and LPDDR3. Not applicable for DDR2 and LPDDR1 devices.