35.7.4 MPDDRC Timing Parameter 0 Register
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
| Name: | MPDDRC_TPR0 |
| Offset: | 0x0C |
| Reset: | 0x20227225 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TMRD[3:0] | TWTR[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TRRD[3:0] | TRP[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRC[3:0] | TWR[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRCD[3:0] | TRAS[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | |
Bits 31:28 – TMRD[3:0] Load Mode Register Command to Activate or Refresh Command
This field defines the delay between a Load mode register command and an Activate or Refresh command in number of DDRCK clock cycles. The number of cycles is between 0 and 15. For low-power DDR2-SDRAM and low-power DDR3-SDRAM, this field is equivalent to tMRW.
Bits 26:24 – TWTR[2:0] Internal Write to Read Delay
This field defines the internal Write to Read command time in number of DDRCK clock cycles. The number of cycles is between 1 and 7.
Bits 23:20 – TRRD[3:0] Active BankA to Active BankB
This field defines the delay between an Activate command in BankA and an Activate command in BankB in number of DDRCK clock cycles. The number of cycles is between 1 and 15.
Bits 19:16 – TRP[3:0] Row Precharge Delay
This field defines the delay between a Precharge command and another command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.
Bits 15:12 – TRC[3:0] Row Cycle Delay
This field defines the delay between an Activate command and a Refresh command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.
Bits 11:8 – TWR[3:0] Write Recovery Delay
This field defines the Write Recovery Time in number of DDRCK clock cycles. The number of cycles is between 1 and 15.
Bits 7:4 – TRCD[3:0] Row to Column Delay
This field defines the delay between an Activate command and a Read/Write command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.
Bits 3:0 – TRAS[3:0] Active to Precharge Delay
This field defines the delay between an Activate command and a Precharge command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.