35.7.23 MPDDRC Monitor Configuration Register

Name: MPDDRC_MCFGR
Offset: 0x60
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
    INFO[1:0]REFR_CALIBREAD_WRITE[1:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
    RUN  SOFT_RESETEN_MONI 
Access R/WR/WR/W 
Reset 000 

Bits 12:11 – INFO[1:0] Information Type

Reports information such as latency and the number of transfers monitored on port x [x = 0..7].

ValueNameDescription
0 MAX_WAIT Information concerning the transfer with the longest waiting time
1 NB_TRANSFERS Number of transfers on the port
2 TOTAL_LATENCY Total latency on the port
3 Reserved

Bit 10 – REFR_CALIB Refresh Calibration

ValueDescription
0 Monitoring does not depend on Auto-refresh mode, Self-refresh mode, Power-down mode, DLL nor calibration impact.
1 Monitoring depends on Auto-refresh mode, Self-refresh mode, Power-down mode, DLL and calibration impact.

Bits 9:8 – READ_WRITE[1:0] Read/Write Access

Used to monitor different types of access.

ValueNameDescription
0 TRIG_RD_WR Read and Write accesses are triggered.
1 TRIG_WR Only Write accesses are triggered.
2 TRIG_RD Only Read accesses are triggered.
3 Reserved

Bit 4 – RUN Control Monitor

ValueDescription
0 Monitoring is halted. All counters are stopped.
1 Monitoring is launched.

Bit 1 – SOFT_RESET Soft Reset

ValueDescription
0 Soft reset is not performed.
1 Soft reset is performed.

Bit 0 – EN_MONI Enable Monitor

ValueDescription
0 Monitor is disabled.
1 Monitor is enabled.