46.11.1.2 LDO Regulator
| Symbol | Parameter | Conditions | Typ. | Units | 
|---|---|---|---|---|
| VREGSCAL | Voltage scaling | min step size for PLx to Ply transition | 5 | mV | 
| Voltage Scaling Period | 1 | µs | 
Note: 1. These values are based on
            simulation. They are not covered by production test limits or characterization.
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Units | 
|---|---|---|---|---|---|---|
| CIN | Input regulator capacitor | Tantalum or electrolitic dielectric | - | 10 | - | µF | 
| Ceramic dielectric X7R | - | 100 | - | nF | ||
| COUT | Output regulator capacitor | Tantalum or electrolitic dielectric | 0.8 | 1 | 1.2 | µF | 
| Ceramic dielectric X7R | - | 100 | nF | |||
| Rserie_COUT | Serial resistance of COUT | - | - | - | 0.5 | Ω | 
Note: 
            
- These values are based on simulation. They are not covered by production test limits or characterization.
 
