32.8.17 ADCON2
Note:
- To correctly calculate an average, the number of samples (set in RPT) must be 2CRS.
- CRS =
3’b111is a reserved option. - This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions.
- See the Computation Modes table for full mode descriptions.
| Name: | ADCON2 |
| Address: | 0x113 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PSIS | CRS[2:0] | ACLR | MD[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W/HC | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – PSIS ADC Previous Sample Input Select bits
| Value | Description |
|---|---|
1 |
FLTR is transferred to PREV at start of conversion |
0 |
ADRES is transferred to PREV at start of conversion |
Bits 6:4 – CRS[2:0] ADC Accumulated Calculation Right Shift Select bits
| Value | Name | Description |
|---|---|---|
| 111 - 000 | MD = b’100’ |
Low-pass filter time constant is 2CRS, filter gain is 1:1 |
| 111 - 000 | MD = b’011’ to
b’001’ |
The accumulated value is right-shifted by CRS (divided by 2CRS)(1,2) |
| xxx | MD = b’000’ to
b’001’ |
These bits are ignored |
Bit 3 – ACLR A/D Accumulator Clear Command bit(3)
| Value | Description |
|---|---|
1 |
The ACC, OV and CNT bits are cleared |
0 |
Clearing action is complete (or not started) |
Bits 2:0 – MD[2:0] ADC Operating Mode Selection bits(4)
| Value | Description |
|---|---|
111 -
101 |
Reserved |
100 |
Low-Pass Filter mode |
011 |
Burst Average mode |
010 |
Average mode |
001 |
Accumulate mode |
000 |
Basic (Legacy) mode |