32.8.19 ADSTAT

ADC Status Register
Note:
  1. If CS = 1, and FOSC < FRC, these bits may be invalid.
Name: ADSTAT
Address: 0x115

Bit 76543210 
 OVUTHRLTHRMATH STAT[2:0] 
Access ROROROR/HS/HCRORORO 
Reset 0000000 

Bit 7 – OV ADC Accumulator Overflow bit

ValueDescription
1 ADC accumulator or ERR calculation have overflowed
0 ADC accumulator and ERR calculation have not overflowed

Bit 6 – UTHR ADC Module Greater-than Upper Threshold Flag bit

ValueDescription
1 ERR > UTH
0 ERR ≤ UTH

Bit 5 – LTHR ADC Module Less-than Lower Threshold Flag bit

ValueDescription
1 ERR < LTH
0 ERR ≥ LTH

Bit 4 – MATH ADC Module Computation Status bit

ValueDescription
1 Registers ADACC, ADFLTR, ADUTH, ADLTH, and the OV bit are updating or have already updated
0 Associated registers/bits have not changed since this bit was last cleared

Bits 2:0 – STAT[2:0]  ADC Module Cycle Multistage Status bits(1)

ValueDescription
111 ADC module is in 2nd conversion stage
110 ADC module is in 2nd acquisition stage
101 ADC module is in 2nd precharge stage
100 Not used
011 ADC module is in 1st conversion stage
010 ADC module is in 1st acquisition stage
001 ADC module is in 1st precharge stage
000 ADC module is not converting
If CS = 1, and FOSC < FRC, these bits may be invalid.