32.8.22 ADCLK
| Name: | ADCLK |
| Address: | 0x118 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CS[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 5:0 – CS[5:0] ADC Conversion Clock Select bits
| Value | Description |
|---|---|
| 11 1111 - 00 0000 | ADC Clock frequency = FOSC/(2*(CS+1)) |
| Name: | ADCLK |
| Address: | 0x118 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CS[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Value | Description |
|---|---|
| 11 1111 - 00 0000 | ADC Clock frequency = FOSC/(2*(CS+1)) |
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