32.8.15 ADCON0
Note:
- This bit requires ON bit to be set.
- If cleared by software while a conversion is in progress, the results of the conversion up to this point will be transferred to ADRES and the state machine will be reset, but the ADIF interrupt flag bit will not be set; filter and threshold operations will not be performed.
| Name: | ADCON0 |
| Address: | 0x111 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ON | CONT | CS | FRM | GO | |||||
| Access | R/W | R/W | R/W | R/W | R/W/HC | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ON ADC Enable bit
| Value | Description |
|---|---|
1 |
ADC is enabled |
0 |
ADC is disabled |
Bit 6 – CONT ADC Continuous Operation Enable bit
| Value | Description |
|---|---|
1 |
GO is retriggered upon completion of each conversion trigger until TIF is set (if SOI is set) or until GO is cleared (regardless of the value of SOI) |
0 |
GO is cleared upon completion of each conversion trigger |
Bit 4 – CS ADC Clock Selection bit
| Value | Description |
|---|---|
1 |
Clock supplied from FRC dedicated oscillator |
0 |
Clock supplied by FOSC, divided according to ADCLK register |
Bit 2 – FRM ADC Results Format/Alignment Selection
| Value | Description |
|---|---|
1 |
ADRES and ADPREV data are right-justified |
0 |
ADRES and ADPREV data are left-justified, zero-filled |
Bit 0 – GO ADC Conversion Status bit(1,2)
| Value | Description |
|---|---|
1 |
ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the CONT bit |
0 |
ADC conversion completed/not in progress |