3.2.17 DIAG_OSCCTRL
The DIAG_OSCCTRL module is designed to verify the correct functionality of the Oscillators Controller (OSCCTRL) through a set of C function calls.
Note: This module contains routines which sets the main clock at
48 MHz. The user would need to call DIAG_OSCCTRL_Initialize to restore the
clock.
Note: DIAG_OSCCTRL_FreqCalibration is not recommended on boards with no external
oscillator (XOSC).
Note: It is not recommended to test the default clock used for
operation.
Note: DIAG_OSCCTRL_ClkSwitchDueToCFD() is deprecated in this
release. See table below and Appendix - FMEDA to Diagnostic API
Mapping
The DIAG_OSCCTRL software test API is mapped to the following safety mechanisms:
| Function | Diagnostic Mechanism | Use Case | Elapse Time (μs)~ |
|---|---|---|---|
| DIAG_OSCCTRL_ClkSwitch() | OSCCTRL_CLOCK_SWITCH | POST | |
| DIAG_OSCCTRL_ClkSwitchDueToCFD() | OSCCTRL_CLOCK_FAILURE_DETECTION | POST | |
| DIAG_OSCCTRL_FDPLL96MEnable() | FDPLL96M_ENABLE | POST / OnDemand | 3.4 |
| DIAG_OSCCTRL_FreqCalibration() | OSCCTRL_CLOCK_CALIBRATION | POST | 5561.33 |
| DIAG_OSCCTRL_Interrupts() |
OSCCTRL_INTERRUPTS | POST | 5432 |
| DIAG_OSCCTRL_OSC48MDisable() | OSC48M_DISABLE | POST | 1013.10 |
| DIAG_OSCCTRL_OSC48MEnable() | OSC48M_ENABLE | POST / OnDemand | 1255.21 |
| DIAG_OSCCTRL_SFRReset() | SFR_RESET | POST | 47.25 |
| DIAG_OSCCTRL_SFRWriteRead() | SFR_WRITE_READ | POST / OnDemand | 43.95 |
| DIAG_OSCCTRL_Startup() | OSCCTRL_STARTUP | POST | 3426.33 |
| DIAG_OSCCTRL_XOSCDisable() | XOSC_DISABLE | POST | 4.50 |
| DIAG_OSCCTRL_XOSCEnable() | XOSC_ENABLE | POST / OnDemand | 4.53 |
Configuring the Diagnostic
DIAG_OSCCTRL does not require additional configuration.
Run-time Pre-requisites
- DIAG_OSCCTRL_ClkSwitch() must not be run if the chosen clock/osc is not present.
- Test that the Osc/Clock is present before testing using:
- DIAG_OSCCTRL_Startup( DIAG_XOSC) and/or
- DIAG_OSCCTRL_FreqCalibration( DIAG_XOSC).
- DIAG_OSCCTRL_ClkSwitchDueToCFD( DIAG_XOSC) will fail if run after
any combination of the following API calls without a reset preceding
it:
- DIAG_OSCCTRL_Startup( DIAG_XOSC)
- DIAG_OSCCTRL_FreqCalibration( DIAG_XOSC).
- DIAG_OSCCTRL_ClkSwitch( DIAG_XOSC)
- XOSC must be at 16Mhz.
Using the Diagnostic
#include "definitions.h"
DIAG_TEST_STATUS DIAG_OSCCTRL_SFRPost(void)
{
DIAG_TEST_STATUS result;
result = DIAG_OSCCTRL_SFRReset(NULL,0,false);
if (result == DIAG_TEST_PASSED)
{
result = DIAG_OSCCTRL_SFRWriteRead(NULL,0,false);
}
return result;
}
int __attribute__((section(".persist"))) or[8];
OSCCTRL_RESET_STATES __attribute__((section(".persist"))) oscctrl_reset_state;
DIAG_TEST_STATUS __attribute__((section(".persist"))) oscctrl_result[NO_OF_OSCCTRL_POST_TESTS];
DIAG_TEST_STATUS DIAG_OSCCTRL_Post( DIAG_OSC_PERIPHS src )
{
DIAG_TEST_STATUS test_status = DIAG_TEST_FAILED;
switch( src )
{
case DIAG_OSCCTRL:
test_status = DIAG_TEST_PASSED; // DIAG_OSCCTRL_Interrupts();
break;
case DIAG_OSC48M_SRC:
// Change clock to FDPLL while testing OSC48M
OSCCTRL_FDPLL_Initialize();
DIAG_GCLK_GeneratorConfig(DIAG_GCLK0, DIAG_FDPLL96M, 1);
test_status = DIAG_OSCCTRL_OSC48MEnable();
if( test_status == DIAG_TEST_PASSED )
{
test_status = DIAG_OSCCTRL_OSC48MDisable();
if( test_status == DIAG_TEST_PASSED )
{
test_status = DIAG_OSCCTRL_Startup(DIAG_OSC48M);
}
}
break;
case DIAG_XOSC_SRC:
test_status = DIAG_OSCCTRL_XOSCEnable();
if( test_status == DIAG_TEST_PASSED )
{
test_status = DIAG_OSCCTRL_XOSCDisable();
if( test_status == DIAG_TEST_PASSED )
{
test_status = DIAG_OSCCTRL_Startup(DIAG_XOSC);
if( test_status == DIAG_TEST_PASSED )
{
test_status = DIAG_OSCCTRL_FreqCalibration(DIAG_XOSC);
}
}
}
break;
case DIAG_FDPLL96M_SRC:
test_status = DIAG_OSCCTRL_FDPLL96MEnable();
if( test_status == DIAG_TEST_PASSED )
{
test_status = DIAG_OSCCTRL_Startup(DIAG_FDPLL96M);
}
break;
default:
break;
}
return test_status;
}
