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21
SmartTime
21.17
Glossary
21.17.3
Capture Edge
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SmartPower
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SmartTime
21
Introduction
21.1
Design Flows with SmartTime
21.2
Starting and Closing SmartTime
21.3
SmartTime Components
21.4
SmartTime Constraint Scenario
21.5
Setting SmartTime Options
21.6
SmartTime Tutorial
21.7
SmartTime Constraints Editor
21.8
SmartTime Timing Analyzer
21.9
Advanced Timing Analysis
21.10
Generating Timing Reports
21.11
Timing Concepts
21.12
Dialog Boxes
21.13
Menus, Tools, and Shortcut Keys
21.14
Data Change History – SmartTime
21.15
Constraints by File Format - SDC Command Reference
21.16
Design Object Access Commands
21.17
Glossary
21.17.1
Arrival Time
21.17.2
Asynchronous
21.17.3
Capture Edge
21.17.4
Clock
21.17.5
Critical Path
21.17.6
Dynamic Timing Analysis
21.17.7
Exception
21.17.8
Explicit Clock
21.17.9
Filter
21.17.10
Launch Edge
21.17.11
Minimum Period
21.17.12
Parallel Paths
21.17.13
Path
21.17.14
Path Details
21.17.15
Path Set
21.17.16
Paths List
21.17.17
Post-layout
21.17.18
Potential Clock
21.17.19
Pre-layout
21.17.20
Recovery Time
21.17.21
Removal Time
21.17.22
Required Time
21.17.23
Requirement
21.17.24
Scenario (Timing Constraints Scenario)
21.17.25
Setup Time
21.17.26
Sink Pin
21.17.27
Skew
21.17.28
Slack
21.17.29
slew rate
21.17.30
Source Pin
21.17.31
STA
21.17.32
Standard Delay Format (SDF)
21.17.33
Static Timing Analysis
21.17.34
Synopsys Design Constraint (SDC)
21.17.35
Timing Constraint
21.17.36
Timing Exception
21.17.37
Timing Requirement
21.17.38
Virtual Clock
21.17.39
WLM
21.18
Revision History
21
Microchip FPGA Support
21
Microchip Information
22
Timer
23
VHDL Vital Simulation
24
Verilog Simulation
25
Technical Support
26
About Microchip
21.17.3 Capture Edge
The clock edge that triggers the capture of data at the end point of a path.
Rev: A
