10.2.4 Divided and Delayed Clock

Use this core to divide down a clock and, if necessary, delay it by a given amount.

This core has two outputs, one global output and an additional output that drives the internal logic. They are equivalent to the GL and Y outputs of a PLL. The divider ranges from 1 to 32.

Supported Families

Divided and Delayed Clock is supported by only the Fusion family.