10.2.9 ProASIC®PLUS PLL

Key Features

  • Clock Delay Adjustment
  • Clock Frequency Synthesis
  • Clock phase shifting
  • MIL operating conditions

    Summary of the menu items available when you generate a PLL for ProASIC® PLUS

    Input Clock Frequency
    Floating point value between 1.5 and 240 MHz
    Feedback
    A radio button to select between Internal, External and Deskewed feedback.

    The clock-conditioning circuitry enables you to implement the feedback clock signal using either the output of the PLL, an internally generated clock or an external clock. When external feedback is selected, an additional port, EXTFB, is made available to the user to drive the feedback. The internal feedback signal can be further delayed by a fixed amount designed to emulate the delay through the chip’s clock tree.

    Configuration
    Dynamic or Static

    In dynamic mode, designers are able to set all the configuration parameters using either the external JTAG port or an internally-defined serial interface. The dynamic-mode PLL can be switched to static mode during operation by just changing a mode selection bit.

Primary Clock

Bypass PLL in Primary Clock
Selecting this checkbox bypasses the PLL for the primary clock. This feature enables you to bypass the PLLCORE functionality and use the surrounding divider and delay elements.
Frequency
Floating point value between 1.5 and 240 MHz. If the specified frequency cannot be achieved, the closest approximate frequency is provided.
Delay
Floating point between -4.0 and 8.0 with increments of 0.25.
Phase Shift
Supports 0, 90, 180 and 270 degrees.

Selecting a phase shift of 90 degrees and an output divider other than 1 causes the configurator to return a message about the actual phase shift being 90 divided by the divider.

Secondary Clock

Bypass PLL in Secondary Clock
Selecting this checkbox bypasses the PLL for the secondary clock.
Input Frequency
Floating point value between 1.5 and 240 MHz.
Frequency
Floating point value between 1.5 and 240 MHz. If the specified value cannot be achieved, the closest approximate frequency is provided.
Delay
Floating point between -4.0 and 8.0 with increments of 0.25.

Use MIL Operating Conditions

MIL operating conditions change the valid range on the Input (Fin) and Output (Fout) frequency requirements.

2 MHz ≤ Fin ≤ 180 MHz

If Fin ≤ 40 MHz, then Fout ≥ 18 MHz. If Fin > 40 MHz, then Fout ≥ 16 MHz. 60 MHz ≤ Fvco ≤ 180 MHz

For more detailed information, refer to Using ProASICPLUS Clock Conditioning Circuits .