10.2.8 IGLOO® and ProASIC®3 Static PLL

The ProASIC3E Clock Conditioning Circuit (CCC) contains a PLL core, delay lines, clock multipliers/dividers, PLL reset generator (you have no control over the reset), global pads and all the circuitry for the selection and interconnection of the “global” pads to the global network. The PLL Core consists of a Phase Detector, L.P. Filter and a 4-Phase VCO.

Related Topics

Key Features

The clock conditioning circuit performs the following basic functions:

  • Clock phase adjustment
  • Clock delay minimization
  • Clock frequency synthesis

In addition it also:

  • Allows access from the global pads to the global network and the PLL block
  • Permits the three global lines on each side of the chip to be driven either by the global pads, core and/or the outputs from the PLL block
  • Allows access from PLL to the core

The block contains several programmable dividers, each of them providing division factors 1, 2, 3, 4……k (where k depends on the number of bits used for the division selection). Overall, you can define a wide range of multiplication and division factors, constrained only by the PLL frequency limits, according to:

m/(n*u)

m/(n*v)

m/(n*w)

The clock conditioning circuit block performs a positive/negative clock delay operation in increments of 200 ps, of up to 6.735 ns (at 1.5V, 25C, typical process) before or after the positive clock edge of the incoming reference clock.

Furthermore, the system allows for the selection of one of four clock phases of fout, at 0, 90, 180 and 270 degrees.

A “Lock” signal is provided to indicate that the PLL has locked on to the incoming signal. A “Power-down” signal switches off the PLL block when it is not used.