10.2.7 Fusion Static PLL

Related Topics

• Fusion Static PLL Functionality
• Fusion Static PLL I/O Description

Key Features

The Static PLL for Fusion contains a PLL core, delay lines, clock multipliers/dividers, PLL reset generator (you have no control over the reset), global pads and all circuitry for the selection and interconnection of the “global” pads to the global network. The PLL Core consists of a Phase Detector, L.P. Filter and a 4-Phase VCO and the following:

• RC Oscillator Clock Source: If you choose RC Oscillator as the clock source the input frequency is fixed at 100 MHz. The divide-by-half feature is available if you bypass the PLL for the primary output.
• Divide by half behavior: Available if clock source is RC Oscillator and PLL is bypassed for the given output (A, B, C). When activated, the output divider (U, V or W) gets divided by 2. Thus if the divider is 3, divide-by-half ON makes the divider 1.5.
• Crystal oscillator clock source: no special configuration options are available if you use the crystal oscillator as your clock source. Select this option if you are using a crystal oscillator as your clock source.
• Availability of output dividers in bypass mode: If you bypass the PLL in the primary output, you can specify an output frequency that is some divisible of the input frequency. The dividing factor must be an integer between 1 and 32.

The Static PLL performs the following basic functions:

• Clock phase adjustment
• Clock delay minimization
• Clock frequency synthesis

In addition, the Static PLL performs the following functions:

• Enables access from the global pads to the global network and the PLL block
• Permits the three global lines on each side of the chip to be driven either by the global pads, core and/or the outputs from the PLL block
• Enables access from PLL to the core

The block contains several programmable dividers, each of them providing division factors 1, 2, 3, 4……k (where k depends on the number of bits used for the division selection). Overall, you can define a wide range of multiplication and division factors, constrained only by the PLL frequency limits, according to:

m/(n*u)

m/(n*v)

m/(n*w)

The clock conditioning circuit block performs a positive/negative clock delay operation in increments of 200 ps, of up to 6.735 ns (at 1.5V, 25C, typical process) before or after the positive clock edge of the incoming reference clock.

Furthermore, the system allows for the selection of one of four clock phases of fout, at 0, 90, 180 and 270 degrees.

A “Lock” signal is provided to indicate that the PLL has locked on to the incoming signal. A “Power-down” signal switches off the PLL block when it is not used.