22.12.4 Delay Filters (max. or min.) / Sorting by Actual or Slack Delays
Setting Minimum or Maximum Delay Filters
Use the Preferences dialog box to filter paths for delays above, below, or between a specified value. Enter your display preferences in the Maximum Delay and Minimum Delay boxes and click OK.
Sorting and Displaying by Actual or Slack Delays
- Actual delay values
- Slack, which is the difference between actual delay and a user-specified
delay (that is, a user-specified constraint)
By default, Timer displays the paths sorted by slack.
Displaying by Actual Delay
The actual delay is the path delay between two points in your design. This is the only way to sort your data if you do not have any timing constraints entered (for information on setting timing constraints, see Constraint Guidelines). If you have entered timing constraints, the actual delay report automatically displays the slack - even if you don't ask for it but the data will always be listed from longest to shortest actual delay.
Actual delay measurements may be calculated before or after layout.
To display Actual delay:
- From the File menu, choose Preferences. This displays the Preferences dialog box
- Select Actual in the Sort By drop-down menu.
- Click OK.
Displaying by Slack Delay
Slack delay is the delay difference between a timing constraint entered in Timer and the actual delay of a path. For example, if a signal takes 20 ns to get from point A to point B and you entered a timing constraint of 15 ns, the Timing Report would list -5 ns slack for that path. Thus, if the slack is negative, then the actual delay did not meet the desired timing by the absolute value of the slack (in ns). Conversely, if the slack value is positive, then the timing constraint was met, with the slack value (in ns) to spare. In a violations report, Timer sorts the data (by default) from longest to shortest slack.
When displaying slack, all the paths without timing constraints are filtered from the reported data. This enables you to quickly determine how well your design meets your timing requirements. This is especially useful for viewing critical delays like register-to-register, clock-to-out, and input-to-register.
