11.2.3.2.1 4:1 Multiplexor

The following examples infer a 4:1 multiplexor using a case statement.

VHDL

--4:1 Multiplexor
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is
port (C, D, E, F : in std_logic;
S :in std_logic_vector(1 downto 0);
mux_out : out std_logic);
end mux;
architecture my_mux of mux is
begin
mux1: process (S, C, D, E, F) begin
case s is
when “00” => muxout <= C;
when “01” => muxout <= D;
when “10” => muxout <= E;
when others => muxout <= F;
end case;
end process mux1;
end my_mux;

Verilog

//4:1 Multiplexor
module MUX (C, D, E, F, S, MUX_OUT);
input C, D, E, F;
input [1:0] S;
output MUX_OUT;
reg MUX_OUT;
always @(C or D or E or F or S)
begin
case (S)
2'b00 : MUX_OUT = C;
2'b01 : MUX_OUT = D;
2'b10 : MUX_OUT = E;
default : MUX_OUT = F;
endcase
end
endmodule